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1. general description the adc1443d is a dual channel 14-bit analog-to-digital converter (adc) with jesd204b-compliant cgvxpress interface op timized for high dynamic performance and low power consumption at sample rates up to 200 msps. pipelined architecture and output error correction ensure the adc1443d is a ccurate enough to guarantee zero missing codes over the entire operating range. supplied from a single 1.8 v source, the adc 1443d has serial outputs compliant with the jesd204b standard over a configurable number of lanes (1 or 2). multiple device synchronization (mds) allows sample-accurate synchronization of the data outputs of multiple adc devices. mds, which is a unique feature of the cgv and cgvxpress technology of nxp semiconductors, guaran tees a maximum skew of one clock period between as many as 16 output lanes from up to eight adc1443d devices. an integrated serial peripheral interface (spi) allows easy configuration of the adc. the device also includes a programmable full-scale to allow a flexible input voltage range of 1 v (p-p) to 2 v (p-p). with excellent dynamic performance from the baseband to input frequencies of up to 250 mhz or more, the adc1443d is ideal fo r use in undersampled multi-carrier, multi-standard communi cation system applications. usin g a pipelined architecture, an output error correction schem e ensures the adc1443d is accurate enough to guarantee zero missing codes over the entire operating range. the adc1443d200 is available in an hlqfn56 package (8 mm ? 8 mm outline). it is supported with customer demo boards. this device is also available in a 12-bit resolution variant with a choice of maximum sampling frequency (125, 160 or 200 msps). 2. features and benefits adc1443d series dual channel 14-bit adc; 125, 160 or 200 msps; jesd204b-compliant cgvx press serial outputs rev. 1 ? 28 september 2011 objective data sheet ? dual channel 14-bit resolution adc ? snr = 72.5 dbfs (typical); f s = 185 msps; f i =190mhz ? sampling rate up to 200 msps ? sfdr = 86 dbc (typical); f s =185msps; f i =190mhz ? jesd204b device subclass 0, 1 and 2 compliant with harmonic clocking and deterministic latency support ? imd3 = 88 dbc (typical); f s =185msps; f i1 = 188.5 mhz; f i2 = 191.5 mhz ? adc multiple device synchronization (mds), cgvxpress feature ? analog input bandwidth of 1 ghz (typical) ? single 1.8 v supply ? typical power dissipation = 1.0 w; f s = 200 msps
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 2 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 3. applications 4. ordering information ? two jesd204b serial output lanes, up to 5 gsps typical ? pin to pin compatible with adc1413d series ? flexible input voltage range from 1 v (p-p) to 2 v (p-p) by 1 db steps ? power-down and sleep modes ? clock input divider from 1 to 8 supports harmonic clocking ? industrial temperature range from ? 40 ? c to +85 ? c ? duty cycle stabilizer (dcs) ? serial peripheral interface (spi) for configuration control and status monitoring ? offset binary and two?s complement output data ? hlqfn56 package; 8 mm ? 8mm ? wireless infrastructure: lte, td-lte, wimax, mc-gsm, cdma, wcdma, td-scdma ? microwave backhaul transceivers ? software defined radio ? aerospace and defense communications and radar systems ? medical non-invasive scanners ? industrial signal analysis instruments ? scientific particle detectors ? general-purpose high-speed applications table 1. ordering information type number f s (msps) package name description version ADC1443D200HD 200 hlqfn56 plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm sot935-2 adc1443d160hd 160 hlqfn56 plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm sot935-2 adc1443d125hd 125 hlqfn56 plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm sot935-2
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 3 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 5. block diagram fig 1. block diagram adc a core pipelined t/h input stage adc b core pipelined t/h input stage adc1443d frame assembly serializer a spi output buffer a serializer b output buffer b scrambler a encoder 8-bit/10-bit a scrambler b encoder 8-bit/10-bit b 8-bit 8-bit inap inam inbp inbm 8-bit 8-bit 10-bit 10-bit syncbp sclk sdio scs_n syncbn cmlbn cmlbp cmlan cmlap 14-bit 14-bit aaa-000417 reference and power management clock divider and duty cycle stabilizer otra otrb sysref clkp clkm vdda vddo agnd ognd vcma vcmb
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 4 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 6. pinning information 6.1 pinning fig 2. pin configuration (sot935-2) adc1443d hlqfn56 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ognd ognd vddo cmlap cmlan vddo ognd ognd vddo cmlbn cmlbp vddo ognd ognd inam inap vcma dnc dnc agnd clkp clkm agnd dnc dnc vcmb inbp inbm vdda vdda sclk sdio scs_n agnd dnc scr_en cfg0/otra cfg1/otrb cfg2 cfg3 vddo ognd vdda sysref (optional) dnc vdda agnd agnd vdda sysrefn sysrefp dnc vddo ognd syncbn syncbp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 aaa-000424 transparent top view terminal 1 index area
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 5 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 6.2 pin description table 2. pin description symbol pin type [1] description inam 1 i channel a complementary analog input inap 2 i channel a analog input vcma 3 o channel a output common voltage dnc 4 - do not connect dnc 5 - do not connect agnd 6 g analog ground clkp 7 i clock input clkn 8 i complementary clock input agnd 9 g analog ground dnc 10 - do not connect dnc 11 - do not connect vcmb 12 o channel b output common voltage inbp 13 i channel b analog input inbm 14 i channel b complementary analog input vdda 15 p analog power supply vdda 16 p analog power supply sclk 17 i spi clock sdio 18 i/o spi data io scs_n 19 i spi chip select agnd 20 g analog ground dnc 21 - do not connect scr_en 22 i scrambler enable cfg0/otra 23 i/o configuration pin 0/out of range a (otra) cfg1/otrb 24 i/o configuration pin 1/out of range b (otrb) cfg2 25 i/o configuration pin 2 cfg3 26 i/o configuration pin 3 vddo 27 p digital output power supply ognd 28 g digital output ground ognd 29 g digital output ground ognd 30 g digital output ground vddo 31 p digital output power supply cmlbp 32 o channel b output cmlbn 33 o channel b complementary output vddo 34 p digital output power supply ognd 35 g digital output ground ognd 36 g digital output ground vddo 37 p digital output power supply cmlan 38 o channel a complementary output cmlap 39 o channel a output
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 6 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. vddo 40 p digital output power supply ognd 41 g digital output ground ognd 42 g digital output ground syncbp 43 i synchronization from field-programmable gate array (fpga) syncbn 44 i complementary synchronization from fpga agnd 45 g analog ground vdda 46 p analog power supply dnc 47 - do not connect sysrefp 48 i positive clock synchronization sysrefn 49 i negative clock synchronization vdda 50 p analog power supply agnd 51 g analog ground agnd 52 g analog ground vdda 53 p analog power supply dnc 54 - do not connect sysref 55 i single-ended ad c clock synchronization vdda 56 p analog power supply table 2. pin description ?continued symbol pin type [1] description
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 7 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 7. limiting values 8. thermal characteristics [1] in compliance with jedec test board, in free air. 9. static characteristics table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage ? 0.3 +2.1 v v ddo output supply voltage ? 0.3 +2.1 v ? v dd supply voltage difference v dda ? v ddo v v i input voltage pins inp, inm, clkp, clkm, sysrefp, and sysrefn; referenced to agnd ? 0.3 v dda +0.3 v pins scs_n, sdio, sclk, cfg, scr_en, syncbp, and syncbn; referenced to ognd ? 0.3 v ddo +0.3 v v o output voltage pin vcm; referenced to agnd ? 0.3 v dda +0.3 v pins otr, cmlp, and cmln; referenced to ognd ? 0.3 v ddo +0.3 v t stg storage temperature ? 55 +125 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature -125 ?c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] k/w r th(j-c) thermal resistance from junction to case [1] k/w table 5. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda analog supply voltage 1.7 1.8 1.9 v v ddo output supply voltage 1.7 1.8 1.9 v i dda analog supply current f s = 200 msps; f i =190mhz -ma i ddo output supply current f s = 200 msps; f i =190mhz -ma
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 8 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs p tot total power dissipation f i =190mhz adc1443d125 - 0.85 w adc1443d160 - 0.95 w adc1443d200 - 1.0 w power-down mode - 10 - mw sleep mode - 130 - mw clock inputs: pins clkp and clkm (ac-coupled; peak-to-peak) v i(clk) clock input voltage lvpecl - ? 0.8 - v lvds - ? 0.35 - v sine differential ? 0.2 ? 1.5 - v lvcmos single - v dda -v c i input capacitance - - pf logic inputs i il low-level input current - - ? a i ih high-level input current - - ? a c i input capacitance - - pf pins sysrefp, sysrefn, syncbp, and syncbn v i(cm) common-mode input voltage 1.2 v v i(dif) differential input voltage - 0.35 - v pins scs_n, sdio, sclk, scr_en and cfg v il low-level input voltage 0 - 0.3v ddo v v ih high-level input voltage 0.7v ddo -v ddo v logic output: pins otr and sdio v ol low-level output voltage 0 - 0.2v ddo v v oh high-level output voltage 0.8v ddo -v ddo v digital outputs: pins cmlap, cmlan, cmlbp, and cmlbn v o(cm) common-mode output voltage - - v v o(dif) differential output voltage default current - ? 400 - mv analog inputs: pins inp and inm i i input current - ? 5- ? a r i input resistance f i =190mhz - - ? c i input capacitance f i =190mhz - 5 - pf v i(cm) common-mode input voltage v inp =v inm 0.9 v b i input bandwidth - 1 - ghz v i(dif) differential input voltage peak-to-peak; full-scale 1 - 2 v common-mode output voltage: pins vcma and vcmb v o(cm) common-mode output voltage - 0.9 - v i o(cm) common-mode output current t amb =25 ? c --4ma accuracy inl integral non-linearity f s = 200 msps; f i =4.43mhz lsb table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 9 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs [1] typical values measured at v dda =v ddo = 1.8 v; t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ?40 ? c to +85 ? c at v dda =v ddo = 1.8 v; v i(dif) = 2 v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. dnl differential non-linearity f s = 200 msps; f i = 4.43 mhz; guaranteed no missing codes lsb e offset offset error - - mv e g gain error full-scale - - % m g(ctc) channel-to-channel gain matching -- % supply psrr power supply rejection ratio mv (p-p) on v dda -- db table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 10 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs 10. dynamic characteristics 10.1 dynamic characteristics table 6. dynamic characteristics [1] symbol parameter conditions adc1443d125 (f s =125msps) adc1443d160 (f s =154msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max ? 2h second harmonic level f i = 5 mhz - - - - - - dbc f i = 30 mhz - - - - - - dbc f i = 70 mhz - - - - - - dbc f i = 140 mhz - - - dbc f i = 170 mhz - - - dbc f i = 190 mhz - - - dbc f i = 230 mhz - - - dbc f i = 310 mhz - - - - - - dbc ? 3h third harmonic level f i = 5 mhz - - - - - - dbc f i = 30 mhz - - - - - - dbc f i = 70 mhz - - - - - - dbc f i = 140 mhz - - - dbc f i = 170 mhz - - - dbc f i = 190 mhz - - - dbc f i = 230 mhz - - - dbc f i = 310 mhz - - - - - - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 11 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs sfdr spurious-free dynamic range ? 1 dbfs f i = 5 mhz - 90 - - 90 - - 90 - dbc f i =30mhz - 88 - - 88 - - 88 - dbc f i =70mhz - 87 - - 87 - - 87 - dbc f i = 140 mhz 86 - 86 - 86 - dbc f i = 170 mhz 86 - 86 - 86 - dbc f i = 190 mhz 86 - 86 - 86 - dbc f i = 230 mhz 85 - 85 - 83 - dbc f i = 310 mhz - 80 - - 80 - - 79 - dbc ? 6 dbfs f i = 5 mhz - - - - - - dbc f i = 30 mhz - - - - - - dbc f i = 70 mhz - - - - - - dbc f i = 140 mhz - - - - - - dbc f i = 170 mhz - - - - - - dbc f i = 190 mhz - - - - - - dbc f i = 230 mhz - - - - - - dbc f i = 310 mhz - - - - - - dbc thd total harmonic distortion f i = 5 mhz - - - - - - dbc f i = 30 mhz - - - - - - dbc f i = 70 mhz - - - - - - dbc f i = 140 mhz - - - - - - dbc f i = 170 mhz - - - - - - dbc f i = 190 mhz - - - - - - dbc f i = 230 mhz - - - - - - dbc f i = 310 mhz - - - - - - dbc table 6. dynamic characteristics [1] ?continued symbol parameter conditions adc1443d125 (f s =125msps) adc1443d160 (f s =154msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 12 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs imd3 third-order intermodulation distortion f i1 = 3.5 mhz; f i2 =6.5mhz - - - - - - dbc f i1 =28.5mhz; f i2 =31.5mhz - - - - - - dbc f i1 =68.5mhz; f i2 =71.5mhz - - - - - - dbc f i1 = 138.5 mhz; f i2 = 141.5 mhz - - - dbc f i1 = 168.5 mhz; f i2 = 171.5 mhz 88 - 88 - 88 - dbc f i1 = 188.5 mhz; f i2 = 191.5 mhz - - 88 - dbc f i1 = 228.5 mhz; f i2 = 231.5 mhz - - - dbc f i1 = 308.5 mhz; f i2 = 311.5 mhz - - - - - - dbc snr signal-to-noise ratio f i = 5 mhz - 74 - - 74 - - 74 - dbfs f i =30mhz - 74 - - 74 - - 74 - dbfs f i = 70 mhz - 73.5 - - 73.5 - - 73.5 - dbfs f i = 140 mhz 73 - 73 - 73.5 - dbfs f i = 170 mhz 72.5 - 72.5 - 72.5 - dbfs f i = 190 mhz 72.5 - 72.5 - 72.5 - dbfs f i = 230 mhz 72 - 72 - 72 - dbfs f i = 310 mhz - 71 - - 71 - - 71 - dbfs table 6. dynamic characteristics [1] ?continued symbol parameter conditions adc1443d125 (f s =125msps) adc1443d160 (f s =154msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 13 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs [1] typical values measured at v dda = v ddo = 1.8 v; t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ?40 ? cto+85 ? c at v dda =v ddo = 1.8 v; v i(dif) = 2 v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. enob effective number of bits f i = 5 mhz - - - - - - bit f i = 30 mhz - - - - - - bit f i = 70 mhz - - - - - - bit f i = 140 mhz - - - - - - bit f i = 170 mhz - - - - - - bit f i = 190 mhz - - - - - - bit f i = 230 mhz - - - - - - bit f i = 310 mhz - - - - - - bit ? ct(ch) channel crosstalk f i = 140 mhz - 100 - - 100 - - 100 - dbc f i = 230 mhz - - - - - - dbc table 6. dynamic characteristics [1] ?continued symbol parameter conditions adc1443d125 (f s =125msps) adc1443d160 (f s =154msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 14 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 10.2 timing 10.2.1 clock timing [1] typical values measured at v dda =v ddo =1.8v; t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ?40 ? c to 85 ? c at v dda =v ddo = 1.8 v; v i(dif) =2v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. 10.2.2 sysref timing table 7. clock and digital output timing characteristics [1] symbol parameter conditions min typ max unit t lat(data) data latency time - - clock cycles t wake wake-up time from power-down mode - - ns from sleep mode - - ns from high impedance - - ns clock timing f s sampling rate adc1443d125 - 125 mhz adc1443d160 - 160 mhz adc1443d200 - 200 mhz f clk clock frequency - 1.2 ghz ? clk clock duty cycle 30 - 70 % t d(s) sampling delay time - - ns fig 3. clock and digital output timing aaa-000418 t d(s) t s n n + 1 n + 2 clkp clkm table 8. sysref timing symbol parameter conditions min typ max unit t su set-up time - - ns t h hold time - - ns
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 15 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 10.2.3 spi timing [1] typical values measured at v dda =v ddo =1.8v; t amb =25 ? c; minimum and maximum values are across the full temperature range t amb = ?40 ? c to +85 ? c at v dda =v ddo =1.8v fig 4. sysref timing aaa-000419 clkp-clkm sysref 50 % 70 % 70 % t su t h table 9. spi timing characteristics [1] symbol parameter conditions min typ max unit t w(sclk) sclk pulse width 40 - - ns t w(sclkh) sclk high pulse width 16 - - ns t w(sclkl) sclk low pulse width 16 - - ns t su set-up time sdio to sclk high 5 - - ns scs_n to sclk high 5 - - ns t h hold time sdio to sclk high 2 - - ns scs_n to sclk high 2 - - ns f clk clock frequency - - 25 mhz fig 5. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) 001aan454 scs_n t w(sclkl) t w(sclkh)
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 16 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 10.3 typical dynamic performances fig 6. 1-tone fft: ? 1dbfs; f i =30mhz; f s = 125 msps fig 7. 1-tone fft: ? 1dbfs; f i = 190 mhz; f s = 125 msps fig 8. 1-tone fft: ? 1dbfs; f i =30mhz; f s =185msps fig 9. 1-tone fft: ? 1dbfs; f i = 190 mhz; f s =185msps fig 10. 2-tone fft: ? 7 dbfs; f i1 =28.5mhz; f i2 = 31.5 mhz; f s =185msps fig 11. 2-tone fft: ? 7 dbfs; f i1 =188.5mhz; f i2 = 191.5 mhz; f s = 185 msps x (x) xx x x aaa-000468 x x x x (x) x x (x) xx x x aaa-000468 x x x x (x) x x (x) xx x x aaa-000468 x x x x (x) x x (x) xx x x aaa-000468 x x x x (x) x x (x) xx x x aaa-000468 x x x x (x) x x (x) xx x x aaa-000468 x x x x (x) x
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 17 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs fig 12. snr as a function of sampling frequency: ? 1dbfs; f i =190mhz fig 13. snr as a function of input frequency: ? 1dbfs; f s =185msps fig 14. snr as a function of input amplitude: f i = 190 mhz; f s =185msps; v i(dif) =2v fig 15. snr as a function of full-scale amplitude: ? 1dbfs; f i = 190 mhz; f s =185msps x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 18 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs fig 16. sfdr as a function of sampling frequency: ? 1dbfs; f i =190mhz fig 17. sfdr as a function of input frequency: ? 1dbfs; f s =185msps fig 18. sfdr as a function of input amplitude: f i = 190 mhz; f s =185msps; v i(dif) =2v fig 19. sfdr as a function of full-scale amplitude: ? 1dbfs; f i = 190 mhz; f s =185msps x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 19 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs fig 20. imd3 as a function of sampling frequency: ? 7dbfs; f i1 = 188.5 mhz; f i2 = 191.5 mhz fig 21. imd3 as a function of input frequency: ? 7dbfs; f s = 185 msps; 3 mhz spacing fig 22. imd3 as a function of input amplitude: f i1 = 188.5 mhz; f i2 = 191.5 mhz; f s = 185 msps; v i(dif) =2v fig 23. imd3 as a function of full-scale amplitude: ? 7dbfs; f i1 = 188.5 mhz; f i2 = 191.5 mhz; f s =185msps x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x x (x) xx x xx x 001aab173 x x x x x x (x) x
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 20 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11. application information 11.1 analog inputs 11.1.1 input stage the analog input of the adc1443d supports a di fferential or a single-ended input drive. optimal performance is achieved using di fferential inputs with respect to the common-mode input voltage (v i(cm) ) on pins inp and inm. the equivalent circuit of the sample and hold input stage, including electrostatic discharge (esd) protection and circuit and package parasitics, is shown in figure 24 . the sample phase occurs when the internal sa mpling clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then held on the sampling capacitors. when the sampling clock signal becomes low, the device enters the hold phase and the voltage information is transmitted to the adc core. 11.1.2 common-mode input voltage (v i(cm) ) set the common-mode input voltage (v i(cm) ) on pins inp and inm externally to 0.9 v for optimal performance. 11.1.3 pin vcm when the input stage is ac-coupled, pin vcm can be used to set the common-mode reference for the analog inputs, for instance, via a transformer middle point. connect a 0.1 ? f filter capacitor between pin vcm and ground to ensure a low-noise common-mode output voltage. fig 24. input sampling circuit 001aan472 inp package esd parasitics switch r on = 15 4 pf 4 pf sampling capacitor sampling capacitor switch r on = 15 inm internal clock internal clock
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 21 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.1.4 programmable full-scale the full-scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) by programming internal reference gain between 0 db and ? 6db in 1db steps. the full-scale range can be set independently via bi ts intref[2:0] of the spi local registers (see table 10 and ta b l e 2 4 ). 11.1.5 anti-kickback circuitry an anti-kickback circuitry (rc-filter in figure 26 ) is required to counteract the effects of the charge injection generated by the sampling capacitance. the rc-filter is also used to filter noise from the signal before it reaches the sampling stage. it is recommended that the capacitor has a value that maximizes noise attenuation without degrading the settling time excessively. fig 25. equivalent schematic of the common-mode reference circuit vcm 0.1 f package esd parasitics 001aan473 common mode reference adc core table 10. reference gain control default values are shown highlighted. intref[2:0] level (db) full-scale (v (p-p)) 000 0 2 001 ? 11.78 010 ? 21.59 011 ? 31.42 100 ? 41.26 101 ? 51.12 110 ? 61 111 reserved x
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 22 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs the input frequency determines the component values. select values that do not affect the input bandwidth. 11.1.6 transformer the input frequency determines the configur ation of the transformer circuit. the configuration shown in figure 27 is suitable for a baseband application. fig 26. anti-kickback circuit table 11. rc coupling versus in put frequency; typical values input frequency range (mhz) r ( ? ) c (pf) 0 to 50 50 to 100 100 to 200 200 to 300 001aan744 r r c inxp inxm fig 27. single transformer configuration (baseband) 001aan667 100 nf 100 nf 100 nf 100 nf 25 25 25 25 12 pf inxp inxm vcmx 100 nf analog input 100 nf
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 23 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs the configuration shown in figure 28 is recommended for high-frequency applications. in both cases, the choice of transformer is a compromise between cost and performance. 11.2 clock input 11.2.1 drive modes the adc1443d series ca n be driven differenti ally (lvpecl, lvds or sine). it can also be driven by a single-ended lvcmos signal connected to either pin clkp or pin clkm (connect the complementar y pin to ground using a ca pacitor). the lvpecl is recommended for an optimal performance. fig 28. dual transformer configuration (high if) 001aan666 100 nf 100 nf 100 nf 100 nf 10 10 3.9 pf inxp inxm vcmx 50 50 50 50 analog input fig 29. lvpecl/lvds diff erential clock input 001aan475 lvpecl / lvds clock input clkp clkm
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 24 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs single-ended or differential clock inputs can be selected via bit diff_se of spi. if single-ended is enabled, the input pin (pin clkm or pin clkp) is selected using control bit se_sel (see table 23 ). a. differential sine clock input b. single-ended sine clock input (with transformer) fig 30. sine clock input a. rising edge lvcmos b. falling edge lvcmos fig 31. lvcmos single-ended clock input sine clock input clkp clkm 005aaa173 sine clock input clkp clkm 005aaa054 lvcmos clock input clkp clkm 005aaa174 005aaa053 lvcmos clock input clkp clkm
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 25 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.2.2 equivalent input circuit figure 32 shows the equivalent circuit of the inpu t clock buffer. the input signal must be ac-coupled and the common-mode voltage of the differential input stage is set via internal 5k ? resistors. 11.2.3 clock input divider the adc1443d contains an input clock divide r that divides the incoming clock (clock frequency f clk ) by a factor of 1 to 8. it output s the sampling clock (sampling frequency f s ) (see bits clk_div[1:0] in table 23 ). this feature delivers a higher clock frequency with better jitter performance, leading to a better snr result once acquisition has been performed. 11.2.4 multi-device synchronization (pins sysref, sysrefn and sysrefp) the multi-device synchronization can be contro lled with a single-ended or a differential sysref signal. a high level on sysref resets the clock divider phase registers. in a multi-device application and when the clock divider fact or is higher than 1, the adc1443d synchronization aligns all sampling clock edges (see ta b l e 8 and figure 4 ). 11.3 digital outputs 11.3.1 digital output buffers the jesd204a/jesd204b standard specifies that both the receiver and the transmitter must be provided by the same supply if they are connected in dc-coupling. fig 32. equivalent input circuit clkp clkm 001aan476 package esd parasitics 5 k v cm(clk) 5 k
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 26 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.3.2 jesd204a/jesd204b serializer 11.3.2.1 digital jesd204a/jesd204b formatter the block placed after the adc cores is used to implement all functionalities of the jesd204a/jesd204b standard. this ensures signal integrity and guarantees the clock and the data recovery at the receiver side. the block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used. fig 33. jesd204a/jesd204b serial output - dc-coupled fig 34. jesd204a/jesd204b serial output - ac-coupled vddo vddo cmlpa/clmpb cmlna/clmnb ognd aaa-000420 12 ma to 26 ma 100 + receiver 50 - vddo cmlpa/clmpb cmlna/clmnb aaa-000421 12 ma to 26 ma 100 10 nf 10 nf + receiver 50 -
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 27 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs fig 35. general overview of the jesd204a/jesd204b serializer frame to octets f octets scrambler tx transport layer cf: position of control bits hd: frame boundary break padding with tail bits (tt) mx(n'xs) bits lx(f) octets l octets n' = n+cs s samples per frame cycle samples stream to lane stream mapping n bits from cr 0 + cs bits for control n bits from cr m?1 + cs bits for control m converters l lanes lane 1 frame to octets f octets scrambler 8-bit/ 10-bit ser tx controller lane 0 8-bit/ 10-bit ser alignment character generator alignment character generator sync~ 005aaa084 fig 36. detailed view of the jesd204a/jesd2 04b serializer with debug functionality n and cs n and cs 00 scr scr prbs 8-bit/ 10-bit 01 00 01 8-bit/ 10-bit prbs 8 8 n + cs n + cs 14 + 1 14 + 1 14 + 1 adc a pll and dll frame clk character clk bit clk 10 10 ser ser 11 10 00 11 10 00 dummy adc_pd adc_pd adc b prbs fsm (frame assembly, character replication; ila, test mode) frame assembly aaa-000423 sync_request 14 + 1 adc_mode[1:0] scr_in_mode scr_in_mode lane_mode[1:0] lane_pol lane_mode[1:0] lane_pol 14 + 1 14 + 1 dummy prbs adc_mode[1:0] 1 f 10f
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 28 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.3.3 out-of-range (otr) an out-of-range signal is provided on pins otra and otrab. the latency of otr is 31 clock cycles. the otr response can be speeded up by enabling fast otr using spi local re gisters (bit fast_otr in ta b l e 3 1 ). in this mode, the latency of otr is reduced to only clock cycl es. the fast otr detection threshold (below full-scale) can be programmed using the spi local registers (bits fast_otr_det[2:0] in ta b l e 3 1 ). 11.3.4 digital offset by default, the adc1443d delivers an output code that corresponds to the analog input. however, it is possible to add a digital of fset to the output code using the spi local registers (bits dig_offset[5:0] in see ta b l e 1 3 and ta b l e 2 7 ). the digital offset adjustment is coded in two?s complement. table 12. fast otr register threshold fast_otr_det[2:0] detection level (db) 000 ? 18.06 001 ? 14.54 010 ? 12.04 011 ? 8.52 100 ? 6.02 101 ? 4.08 110 ? 2.5 111 ? 1.16 table 13. digital offset adjustment default values are shown highlighted. dig_offset[5:0] digital offset adjustment (lsb) 10 0000 ? 32 10 0001 ? 31 ... ... 11 1111 ? 1 00 0000 0 00 0001 +1 ... ... 01 1110 +30 01 1111 +31
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 29 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.3.5 test patterns the adc1443d can be configured to transmit on e of a number of predefined test patterns using the spi local registers (bits test_pat_sel[2:0] in table 14 and table 28 ). the selected test pattern is transmitted regardless of the analog input. a custom test pattern can be defined using the spi local registers (bits test_pat_user[13:6] in ta b l e 2 9 and bits test_pat_user[5:0] in ta b l e 3 0 ). 11.3.6 output data format selection the adc1443d output data format can be selected (offset binary, two?s complement or gray code) using the spi local regi sters (bits data_format[1:0] in ta b l e 2 6 ). 11.3.7 output codes versus input voltage table 14. digital test pattern selection default values are shown highlighted. test_pat_sel[2:0] digital test pattern 000 off 001 mid code 010 min code 011 max code 100 toggle ?1111..1111?/?0000..0000? 101 custom test pattern 110 ?1010..1010? 111 ?0101..0101? table 15. output codes v inp ? v inm offset binary two?s complement gray code otr < ? 1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 1 ? 1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 0 ? 0.99987793 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 0 ? 0.99975586 00 0000 0000 0010 00 0000 0000 0010 00 0000 0000 0011 0 ... ... ... ... 0 ? 0.00024414 01 1111 1111 1110 11 1111 1111 1110 01 0000 0000 0001 0 ? 0.00012207 01 1111 1111 1111 11 1111 1111 1111 01 0000 0000 0000 0 +0.00012207 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 0 +0.0.00024414 10 0000 0000 0001 00 0000 0000 0001 11 0000 0000 0001 0 ... ... ... ... 0 +0.99975586 11 1111 1111 1101 01 1111 1111 1101 10 0000 0000 0011 0 +0.99987793 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 0 +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0 > +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 30 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.4 configuration pins (c fg0, cfg1, cfg2, cfg3) the configuration pins are only active as inpu ts at start-up. the values on those pins are read once to set up the device. then the pins become outputs (otra and otrb) and any change in the configuration is applied by spi. [1] f: octets per frame clock cycle hd: high-density mode k: frame per multi-frame m: converters per device l: lane per converter device cs: number of control bits per conversion sample cf: control words per frame clock cycle and link s: number of samples transmitted per single converter per frame cycle table 16. jesd204a/jesd204b configuration table cfg_setup[3:0] adc a adc b lane 0 lane 1 f [1] hd [1] k [1] m [1] l [1] comment cs [1] cf [1] s [1] 0 0000 on on on on 20922(f ? k) ? 17 1 0 1 1 0001 on on on off 4 0 5 2 1 (f ? k) ? 17 1 0 1 2 0010 on on off on 40521(f ? k) ? 17 1 0 1 3 0011 reserved 4 0100 reserved 5 0101 on off on off 2 0 9 1 1 (f ? k) ? 17 1 0 1 60110 on off off on 20911(f ? k) ? 17 1 0 1 70111 off on on off 2 0 9 1 1 (f ? k) ? 17 1 0 1 8 1000 off on off on 20911(f ? k) ? 17 1 0 1 9 1001 reserved 10 1010 reserved 11 1011 reserved 12 1100 reserved 13 1101 reserved 14 1110 reserved 15 1111 off off off off 2 0 9 2 2 chip power-down 101
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 31 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.5 serial peripheral interface (spi) 11.5.1 register description the adc1443d serial interface is a synchr onous serial communications port, which allows easy interfacing with many commonly used microprocess ors. it provides access to the registers controlling t he operation of the chip. the register bits are either global or local functions: ? a global function operates over the full ic behavior. a local function operates on one or several previously selected channels on ly. if a channel is selected, the next write command in the local regist ers applies to the selected channel. the write command has no impact on channels that are not se lected. this makes it possible to apply different configurations on each channel by first selecting a specific channel and then all the related settings. ? select only one channel during a read oper ation of the local re gisters. if several channels are selected, the read operation occurs on the channel a. programming all registers at the same time is required: ? the ic allows the storage of a set of se ttings for the addresses 06h to 23h, which enables the configuration of all registers simultaneously by setting bit transfer to high (see ta b l e 3 2 ). this bit is autoclearing. this function can be disabled using spi (bit trans_dis in ta b l e 3 2 ). the registers are then updated at each write operation. ? the transfer function does not apply to a read operation. the spi interface is configured as a 3-wire ty pe: pin sdio is the bidirectional pin, pin sclk is the serial clock input and scs_n is the chip select pin. a low level on pin scs_n initiates each re ad/write operation. a minimum of 3 bytes is transmitted (two instruction bytes and at least 1 data byte; see table 18 ). ? bit r/w indicates whether it is a read (when high) or a write (when low) operation. ? bits w1 and w0 indicate the number of bytes to be transferred after both instruction bytes (see ta b l e 1 8 ). table 17. instruction bytes for the spi bit: 7 (msb) 6 5 4 3 2 1 0 (lsb) description r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 18. number of data bytes transferred w1 w0 number of bytes transferred 001 byte 012 bytes 103 bytes 1 1 4 or more bytes
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 32 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs ? bits a12 to a0 indicate the address of the register being accessed. if it concerns a multiple byte transfer, this ad dress is the first register a ccessed. an addr ess counter is increased to access subsequent addresses. the steps for a data transfer are: 1. communication starts with the first rising edge on pin sclk after a falling edge on pin scs_n. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the data. its length varies, but it is always a multiple of 8 bits. the msb is always sent first (for instruction and data bytes). 4. a rising edge on pin scs_n indicates the end on data transmission. fig 37. spi mode timing scs_n sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data) 001aan743
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 33 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs 11.5.2 register allocation map ta b l e 1 9 shows an overview of all registers. table 19. register allocation map addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex adc control registers 0000h chip_reset rw sw_rst[7:0] 0000 0000 00h 0001h chip_id r chip_id[7:0] [1] 0100 0011 43h 0005h chip_reset r/w s w_rst - - - - - - - 0000 0000 00h 0006h [2] op_mode r/w - - - - - - op_mode[1:0] [3] 0000 0000 00h 0007h clk_cfg r/w - - - se_sel diff _se clk_div[2:0] 0000 0000 00h 0008h internal_ref r/w - - - - - intref[2:0] 0000 0000 00h 0009h channel_sel r/w - - - - - - adc_b adc_a 0000 1111 0fh 0011h output_cfg r/w - - - - - data_swap data_format[1:0] 0000 0000 00h 0013h dig_offset r/w dig_offset[5:0] - - 0000 0000 00h 0014h test_cfg_1 r/w - - - - - test_pat_sel[2:0] 0000 0000 00h 0015h test_cfg_2 r/w test_pat_user[13:6] 0000 0000 00h 0016h test_cfg_3 r/w test_pat_user[5:0] - - 0000 0000 00h 0017h otr_cfg r/w - - - - fast_ otr fast_otr_det[2:0] 0001 0100 14h 00ffh trans_cfg r/w trans_ dis transfer - - - - - - 0000 0000 00h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 34 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs jesd204a/jesd204b control 0800h ip_digital_id r/w 1 0 1 0 ip_dig_ id[3] ip_dig_ id[2] ip_dig_ id[1] ip_dig_ id[0] 1010 0000 0801h ip_status r/w rxsync_ err_flg res_ bonding[2:0] --por_tstpll_ inl 0000 0000 0802h ip_reset r/w sw_ rst ---fsm_sw _rst - - - 0000 0000 0803h ip_cfg_setup r/w - - - - cfg_ stp[3:0] 0000 **** 0805h ip_ctrl1 r/w adc_ dir_ scsb tristate_ cfg_path sync_pol sync_se en_ rssync_ err rev_scr_in rev_ enc_in rev_ ser_in 0000 0000 0806h ip_ctrl2 r/w scr_clk _dis precomp_ clk_dis mdssync_ clk_dis mdsdata _clk_dis lane_map[1:0] swp_ ?lane_1_2 swp_ adc_0_1 0000 **** 0807h ip_ctrl3 r/w mds_en sync_lat[2:0] data_lat[3:0] 0000 0000 0808h ip_sysref_tout r/w sysref_to[7:0] 0000 0000 0809h ip_scr1 r/w lsb_init[7:0] 0000 0000 080ah ip_scr2 r/w msb_init[7:0] 1111 1111 080bh ip_prbs_ctrl r/w - - - - - prbs_on_ sync prbs_type[1:0] 0000 0000 080ch ip_pll_ctrl1 r/w ck_ det_cur[1:0] icp_int[1:0] pll_ ref_sel pll_inl_ byp pll_tst_ en pll_pd 0000 00** 080dh ip_pll_ctrl2 r/w pll_ca l_cntr[7:3] pll_p[2:0] 1000 0000 0816h ip_debug_out1 r/w - - - - - - pat_out[9:8] 0000 0010 0817h ip_debug_out2 r/w pat_out[7:0] 1010 1010 0818h ip_debug_in1 r/w pat_in[15:8] 1010 1010 table 19. register allocation map ?continued addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 35 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 200 msps; jesd204a/b serial outputs [1] the read-only and reserved registers. [2] the registers influenced by the transfer function. [3] the local registers. 0819h ip_debug_in2 r/w pat_in[7:0] 0000 0010 081ah ip_spare_debug r/w spare_dbg[7:5] sync_ tap_en sync_tap_sel[3:0] 0860h outbuf01_ctrl r/w ctrl_spar e[2:0] preemph_ctrl[2:0] preemph _pd full_ pd 0000 0000 0861h outbuf02_ctrl r/w ctrl_spar e[2:0] preemph_ctrl[2:0] preemph _pd full_ pd 0000 0000 0862h outbuf03_ctrl r/w ctrl_spar e[2:0] preemph_ctrl[2:0] preemph _pd full_ pd 0000 0000 0863h outbuf04_ctrl r/w ctrl_spar e[2:0] preemph_ctrl[2:0] preemph _pd full_ pd 0000 0000 086ah outbuf01_swing r/w swin g_spare[2:0] swing[4:0] 0000 01** 086bh outbuf02_swing r/w swin g_spare[2:0] swing[4:0] 0000 01** 086ch outbuf03_swing r/w swin g_spare[2:0] swing[4:0] 0000 01** 086dh outbuf04_swing r/w swin g_spare[2:0] swing[4:0] 0000 01** 0871h lane0_0_ctrl r/w lane_lat[2:0] lane_mode[1:0] lane_pol lane_clk _pos_ edge lane_ pd 0000 000* 0872h lane1_0_ctrl r/w lane_lat[2:0] lane_mode[1:0] lane_pol lane_clk _pos_ edge lane_ pd 0000 000* 0890h adca_0_ctrl r/w - - adc_mode[1:0] - - - adc_ pd 0000 0000 0891h adcb_0_ctrl r/w - - adc_mode[1:0] - - - adc_ pd 0000 0000 table 19. register allocation map ?continued addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 36 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.5.3 detailed register description the tables in this section contain detailed descriptions of the registers. 11.5.3.1 adc control registers [1] local register. table 20. chip_reset register (a ddress 0000h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 sw_rst r/w - resets global and local registers for any value ?1? written at any bit (autoclear). table 21. chip_reset register (a ddress 0005h) bit description default settings are shown highlighted. bit symbol access value description 7 sw_rst r/w resets global and local registers 0 no reset 1 performs a reset to the default values (autoclear) 6 to 0 - - - not used table 22. op_mode register (address 0006h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - not used 1 to 0 op_mode[1:0] [1] r/w operating mode for the selected channel 00 normal (power-up) 01 power-down 10 sleep 11 not used table 23. clk_cfg register (address 0007h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 - - - not used 4 se_sel r/w single-ended clock input pin selection 0clkp 1clkm 3 diff_se r/w differential/single-ended clock input selection 0 fully differential 1 single-ended
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 37 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs [1] local register 2 to 0 clk_div[1:0] r/w cl ock divider selection 000 divide by 1 001 divide by 2 010 divide by 3 011 divide by 4 100 divide by 5 101 divide by 6 110 divide by 7 111 divide by 8 table 23. clk_cfg register (address 0007h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 24. internal_ref register (address 0008h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 to 0 intref[2:0] [1] r/w - see table 10 table 25. channel_sel register (address 0009h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - not used 1 adc_b r/w channel b selection for next spi operation in local registers 0 not selected 1 selected 0 adc_a r/w channel a selection for next spi operation in local registers 0 not selected 1 selected table 26. output_cfg register (address 0011h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 data_swap [1] r/w output data bits swapped 0 no swapping 1 msbs swapped with lsbs
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 38 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs [1] local register [1] local register [1] local register [1] local register [1] local register 1 to 0 data_format[1:0:] [1] r/w output data format 00 offset binary 01 two?s complement 10 gray code 11 offset binary table 26. output_cfg register (address 0011h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 27. dig_offset register (a ddress 0013h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 dig_offset[7:0] [1] r/w - see table 13 1 to 0 - - - not used table 28. test_cfg_1 register (address 0014h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 to 0 test_pat_sel[2:0] [1] r/w - see table 14 table 29. test_cfg_2 register (address 0015h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 test_pat_user[13:6] [1] r/w - custom digital test pattern (bits 13 to 6) table 30. test_cfg_3 register (address 0016h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 test_pat_user[5:0] [1] r/w - custom digital test pattern (bits 7 to 0) 1 to 0 - - - not used
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 39 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs [1] local register table 31. otr_cfg register (address 0017h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 - - - not used 3 fast_otr [1] r/w selection otr full-scale/ fast otr 0 otr full-scale 1 fast otr 2 to 0 fast_otr_det[3:0] [1] r/w - table 32. trans_cfg register (a ddress 00ffh) bit description default settings are shown highlighted. bit symbol access value description 7 trans_dis r/w disable transfer function 0 transfer function active 1 registers updated on a write command 6 transfer r/w updates the registers with the written settings 0 settings are stored 1 registers updated (autoclear) 5 to 0 - - - not used
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 40 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 11.5.3.2 jesd204a/jesd204b control registers table 33. ip_digital_id register (address 0800h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 - - 1010 not used 3 to 0 ip_dig_id[3:0] r/w **** table 34. ip_status register (address 0801h) bit description default settings are shown highlighted. bit symbol access value description 7 rxsync_err_flg r/w 0 6 to 4 res_bond ing[2:0] r/w 000 3 to 2 - - 0 not used 1 por_tst r/w 0 power-on reset 0 pll_inlock r/w 0 table 35. ip_reset register (a ddress 0802h) bit description default settings are shown highlighted. bit symbol access value description 7 sw_rst r/w 0 initiates a software reset of the jedec204a/jesd204b unit 6 to 4 - - 000 not used 3 fsm_sw_rst r/w 0 initiates a software reset of the internal state machine of jedec204a/jesd204b unit 2 to 0 - - 000 not used table 36. ip_cfg_setup register (address 0803h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 to 0 cfg_setup[3:0] r/w **** table 37. ip_ctrl1 register (add ress 0805h) bit description default settings are shown highlighted. bit symbol access value description 7 adc_direct_scsb r/w 0 6 tristate_cfg_path r/w 0 (1 > 0) 5 sync_pol r/w 0 synchronization polarity 4 sync_se r/w 0 3 en_rssync_err r/w 1 2 rev_scr_in r/w 0 1 rev_enc_in r/w 0 0 rev_ser_in r/w 1
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 41 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs table 38. ip_ctrl2 register (add ress 0806h) bit description default settings are shown highlighted. bit symbol access value description 7 scr_clk_dis r/w 0 6 precomp_clk_dis r/w 0 5 mdssync_clk_dis r/w 0 4 mdsdata_clk_dis r/w 0 3 to 2 lane_m apping[1:0] r/w ** 1 swp_lane_1_2 r/w * 0 swp_adc_0_1 r/w * table 39. ip_ctrl3 register (add ress 0807h) bit description default settings are shown highlighted. bit symbol access value description 7mds_en r/w 0 6 to 4 sync_latency[2:0] r/w 000 3 to 0 data_latency[3:0] r/w 0000 table 40. ip_sysref_time_out register (address 0808h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 sysref_to[7:0] r/w 0000 0000 table 41. ip_scrambler1 register (address 0809h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 lsb_init[7:0] r/w 0000 0000 table 42. ip_scrambler2 register (address 080ah) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 msb_init[7:0] r/w 1111 1111 table 43. ip_prbs_ctrl register (address 080bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 prbs_on_sync r/w 0 1 to 0 prbs_type[1:0] r/w 00 table 44. ip_pll_ctrl1 register (address 080ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ck_det_cur[1:0] r/w 00 5 to 4 icp_int[1:0] r/w 00 3 pll_ref_sel r/w 0
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 42 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 2 pll_inlock_bypass r/w 0 1 pll_tst_en r/w * 0 pll_pd r/w * table 44. ip_pll_ctrl1 register (address 080ch) bit description ?continued default settings are shown highlighted. bit symbol access value description table 45. ip_pll_ctrl2 register (address 080dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 pll_cal_cntr[7:3] r/w 10000 2 to 0 pll_p[2:0] r/w 000 table 46. ip_debug_out1 register (a ddress 0816h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - 000000 not used 1 to 0 pattern_out[9:8] r/w 10 table 47. ip_debug_out2 register (a ddress 0817h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_out[7:0] r/w 1010 1010 table 48. ip_debug_in1 register (address 0818h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_in[15:8] r/w 1010 1010 table 49. ip_debug_in2 register (address 0819h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_in[7:0] r/w 0000 0010 table 50. ip_spare_debug register (address 081ah) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 spare_debug[7:5] r/w 4 sync_tap_en r/w 3 to 0 sync_tap_sel[3:0] r/w
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 43 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs table 51. ip_outbuf01_ctrl register (address 0860h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 ctrl_spare[2:0] r/w 000 4 to 2 preemph_ctrl[2:0] r/w 000 1 preemph_pd r/w 0 0 full_pd r/w 0 table 52. ip_outbuf02_ctrl register (address 0861h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 ctrl_spare[2:0] r/w 000 4 to 2 preemph_ctrl[2:0] r/w 000 1 preemph_pd r/w 0 0 full_pd r/w 0 table 53. ip_outbuf03_ctrl register (address 0862h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 ctrl_spare[2:0] r/w 000 4 to 2 preemph_ctrl[2:0] r/w 000 1 preemph_pd r/w 0 0 full_pd r/w 0 table 54. ip_outbuf04_ctrl register (address 0863h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 ctrl_spare[2:0] r/w 000 4 to 2 preemph_ctrl[2:0] r/w 000 1 preemph_pd r/w 0 0 full_pd r/w 0 table 55. ip_outbuf01_swing regist er (address 086ah) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 swing_spare[2:0] r/w 000 4 to 0 swing[4:0] r/w 001** table 56. ip_outbuf02_swing regist er (address 086bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 swing_spare[2:0] r/w 000 4 to 0 swing[4:0] r/w 001**
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 44 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs table 57. ip_outbuf03_swing regist er (address 086ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 swing_spare[2:0] r/w 000 4 to 0 swing[4:0] r/w 001** table 58. ip_outbuf04_swing regist er (address 086dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 swing_spare[2:0] r/w 000 4 to 0 swing[4:0] r/w 001** table 59. ip_lane0_0_ctrl register (address 0871h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 lane_late ncy[2:0] r/w 000 4 to 3 lane_mode[1:0] r/w 00 2 lane_pol r/w 0 1 lane_clk_pos_edge r/w 0 0 lane_pd r/w * table 60. ip_lane1_0_ctrl register (address 0872h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 lane_late ncy[2:0] r/w 000 4 to 3 lane_mode[1:0] r/w 00 2 lane_pol r/w 0 1 lane_clk_pos_edge r/w 0 0 lane_pd r/w * table 61. ip_adca_0_ctrl register (address 0890h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 4 adc_mode[1:0] r/w 00 3 to 1 - - 000 not used 0 adc_pd r/w 0 table 62. ip_adcb_0_ctrl register (address 0891h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 4 adc_mode[1:0] r/w 00 3 to 1 - - 000 not used 0 adc_pd r/w 0
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 45 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 12. package outline fig 38. package outline sot935-2 (hlqfn56) references outline version european projection issue date iec jedec jeita sot935-2 sot935-2_po 11-08-16 11-08-18 unit mm max nom min 1.40 0.30 5.85 8.1 6.45 6.5 0.50 0.1 a dimensions hlqfn56r: plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 x 8 x 1.35 mm sot935-2 bd 8.1 d h ee h ey 1 e 1 6.5 e 2 ll 1 0.05 vw 0.05 0.55 0.10 y 1.35 0.25 5.80 8.0 6.40 0.5 8.0 0.05 0.1 0.45 0.00 1.25 0.20 5.75 7.9 6.35 7.9 0 10 mm scale c y c y 1 x detail x a terminal 1 index area b a e d e 2 e 1 e e 1/2 e b terminal 1 index area d h l 1 l e h 14 1 43 56 42 29 28 15 ac b v wc
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 46 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 13. abbreviations table 63. abbreviations acronym description adc analog-to-digital converter cdma code division multiple access dav data valid esd electrostatic discharge fft fast fourier transform gsm global system for mobile communications imd3 third order intermodulation product lsb least significant bit lte long-term evolution lvds ddr low voltage differential signaling double data rate lvpecl low-voltage positive emitter-coupled logic mimo multiple input multiple output msb most significant bit otr out-of-range sfdr spurious-free dynamic range spi serial peripheral interface snr signal-to-noise ratio td-scdma time division-synchronous code division multiple access wcdma wideband code division multiple access wimax worldwide interoperability for microwave access
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 47 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 14. revision history table 64. revision history document id release date data sheet status change notice supersedes adc1443d_ser v.1.1 20110928 objective data sheet - adc1443d_ser v.1 modifications: ? section 1 ? general description ? has been updated. ? section 2 ? features and benefits ? has been updated. ? section 3 ? applications ? has been updated. ? table 5 has been updated. adc1443d_ser v.1 20110901 objective data sheet - -
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 48 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
adc1443d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 28 september 2011 49 of 50 nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors adc1443d series dual 14-bit adc; 125, 160 or 20 0 msps; jesd204a/b serial outputs ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 28 september 2011 document identifier: adc1443d_ser please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 thermal characteristics . . . . . . . . . . . . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2.2 sysref timing. . . . . . . . . . . . . . . . . . . . . . . . 14 10.2.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.3 typical dynamic performances . . . . . . . . . . . . 16 11 application information. . . . . . . . . . . . . . . . . . 20 11.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.1 input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.2 common-mode input voltage (v i(cm) ) . . . . . . . 20 11.1.3 pin vcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.4 programmable full-scale . . . . . . . . . . . . . . . . . 21 11.1.5 anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 21 11.1.6 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.2.1 drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.2.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 25 11.2.3 clock input divider . . . . . . . . . . . . . . . . . . . . . 25 11.2.4 multi-device syn chronization (pins sysref, sysrefn and sysrefp). . . . . . . . . . . . . . . 25 11.3 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.3.1 digital output buffers. . . . . . . . . . . . . . . . . . . . 25 11.3.2 jesd204a/jesd204b serializer . . . . . . . . . . 26 11.3.2.1 digital jesd204a/jesd204b formatter . . . . . 26 11.3.3 out-of-range (otr) . . . . . . . . . . . . . . . . . . . 28 11.3.4 digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.3.5 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3.6 output data format selecti on. . . . . . . . . . . . . . 29 11.3.7 output codes versus input voltage . . . . . . . . . 29 11.4 configuration pins (cfg0, cfg1, cfg2, cfg3) . . . . . . . . . . . . . 30 11.5 serial peripheral interfac e (spi) . . . . . . . . . . . 31 11.5.1 register description . . . . . . . . . . . . . . . . . . . . 31 11.5.2 register allocation map . . . . . . . . . . . . . . . . . 33 11.5.3 detailed register description . . . . . . . . . . . . . 36 11.5.3.1 adc control registers. . . . . . . . . . . . . . . . . . . 36 11.5.3.2 jesd204a/jesd204b control registers . . . . 40 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 45 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 47 15 legal information . . . . . . . . . . . . . . . . . . . . . . 48 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 48 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 48 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 49 16 contact information . . . . . . . . . . . . . . . . . . . . 49 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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